Precision for High-Density Interconnect
IC Substrate
Precision Packaging for High-Reliability Semiconductors
Puruidy delivers advanced IC Substrates designed for aerospace, defense, medical, and telecommunications applications. Leveraging mSAP technology and ultra-fine line capabilities, we enable high-density interconnects, low-loss signal integrity, and exceptional thermal reliability—engineered for the most demanding mission-critical environments.
IC Substrate : The Foundation of Advanced Semiconductor Packaging
IC Substrates serve as the critical interconnect hub in modern chip packaging, delivering three essential functions: chip protection, electrical interconnection, and thermal management. Engineered to surpass conventional PCB capabilities, they enable ultra-high-density connectivity between chips and mainboards.
Leveraging advanced materials such as ABF and BT, Puruidy’s IC Substrates support ultra-fine circuits with line/space down to 8μm. Integrated micro-bumps and redistribution layers ensure sub-micron I/O accuracy, while rigorous signal and power integrity control enables advanced architectures including 2.5D/3D integration and chiplets. This makes our substrates the enabling technology for AI, high-performance computing, and premium communication chips.
IC Substrate Manufacturing Capabilities
| Feature | Capability |
| Substrate Types | Core-type, Coreless, Embedded Trace Substrate (ETS) |
| Materials | ABF (Ajinomoto Build-up Film), BT (Bismaleimide Triazine), High-speed/high-frequency variants |
| Layer Count | 2–12 layers (core + build-up layers); 2–6 layers typical for mass production |
| Build-up Structure | 1+N+1, 2+N+2, up to 4+N+4 (evaluation required beyond 6 build-up layers) |
| Min. Line / Space | 15μm / 15μm (mass production) 10μm / 10μm (evaluation) 8μm / 8μm (under development for advanced applications) |
| Min. Copper Thickness (finished) | 5μm – 35μm (depending on layer type and design) |
| Substrate Thickness | 0.2mm – 1.5mm (core thickness: 0.05mm–0.8mm; total thickness includes build-up layers) |
| Max. Panel Size | 510mm × 515mm (for standard substrate manufacturing) Smaller panel sizes (e.g., 250mm × 300mm) often used for higher precision |
| Min. Laser Drilled Via (microvia) | 50μm (mass production) 40μm (evaluation) Dielectric thickness per layer: 20μm–60μm |
| Laser Via Aspect Ratio | ≤ 1:1 (typical) |
| Min. Mechanical Drilling | 0.15mm (for core through holes) |
| Core Through Hole Aspect Ratio | ≤ 8:1 |
| RDL (Redistribution Layer) Capability | Supported; line/space down to 8μm/8μm with semi-additive process (SAP/mSAP) |
| I/O Pitch (Bump Pitch) | 80μm (mass production) 60μm (evaluation) 40μm (under development) |
| Surface Finishes | ENIG, ENEPIG, Electrolytic Ni/Au (for wire bonding), OSP, Immersion Ag, Immersion Sn |
| Solder Mask / Dielectric | Photo-imageable dielectric (PID), ABF build-up film, solder mask on outermost layer (if required) |
| Via Fill | Copper-filled microvias (via-in-pad), resin-filled, or unfilled as per design |
| Warpage Control | ≤ 0.5% (or < 200μm across panel), controlled through material selection and symmetric stack-up |
| Electrical Testing | Flying probe, fixture-based, Kelvin testing for low-resistance verification |
| Reliability Qualifications | MSL (Moisture Sensitivity Level) 1–3, TCT (Thermal Cycling Test), HAST, uHAST, Td (decomposition temperature), CTE (Coefficient of Thermal Expansion) matching |
Featured Product Solutions
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application scene
Our products are highly stable, safe, and reliable, and are widely used in the aerospace, defense, medical, and telecommunications sectors.
